The present invention relates to a semiconductor integrated circuit having a plurality of macros integrated therein (hereinafter referred to “multi macro integrated semiconductor IC” for brevity) on a semiconductor chip and, more specifically, relates to a control circuit thereof for performing data transfer and testing of macro circuits, and is intended to be used in an LSI (Large Scale Integration) having a plurality of DRAM circuits integrated therein, a DRAM embedded logic LSI having a plurality of DRAM circuits and logic circuits integrated together therein, etc.
As multi macro integrated LSI circuits having a plurality of macro circuits integrated therein, there are DRAM having a plurality of DRAM circuits (macro circuits) integrated therein, a DRAM embedded logic LSI having a DRAM circuit (macro circuit) and a macro circuit of other kind, for example a logic circuit, integrated therein, and the like.
Conventionally, in a LSI having a plurality of DRAM circuits integrated therein, when the plurality of DRAM circuits are to be tested, each of the DRAM circuits is tested independently from each other.
FIG. 7 is a view showing an access pattern for two DRAM circuits DRAM1, DRAM2 in the conventional LSI that is formed of a plurality of DRAM circuits and is, specifically, a view showing a sequence of access in the case where the two DRAM circuits DRAM1, DRAM2 are successively tested. FIG. 8 is a flowchart in the case where the two DRAM circuits are tested in the access pattern of FIG. 7.
In the access pattern, first, the memory cells of a first row in the first DRAM circuit DRAM1 are sequentially accessed over the whole columns. Next, the memory cells of a second row in the first DRAM circuit DRAM1 are sequentially accessed over the whole columns. Such access is repeated from the following row to the last row of the first DRAM circuit DRAM1. After the completion of the access to the first DRAM circuit DRAM1, an access is performed to the memory cells of the second DRAM circuit DRAM2 in the same manner as in the above-mentioned first DRAM circuit DRAM1. That is, the memory cells of a first row in the second DRAM circuit DRAM2 are sequentially accessed over the whole columns. Next, the memory cells of the second row in the second DRAM circuit DRAM2 are sequentially accessed over the whole columns. Such access is repeated from the following row to the last row of the second DRAM circuit DRAM2.
In this case, for each of the first and second DRAM circuits DRAM1 and DRAM2, every time each DRAM circuit is accessed, it is necessary to set an access period tRAS to activate the bank active signal BACT and then select one of the rows of each DRAM circuit to conduct read operation for the memory cells successively over the columns and a precharge period tRP to conduct a bit line precharge operation in response to a bit line precharge signal BPRC. That is, for the first DRAM circuits DRAM1, every time each row of the first DRAM circuits DRAM1 is accessed, it is necessary to set the access period tRAS to activate the bank active signal BACT and then select one of the rows of the DRAM circuit DRAM1 to conduct read operation for the memory cells successively over the columns and the precharge period tRP to conduct a bit line precharge operation in response to a bit line precharge signal BPRC. Similarly, for the second DRAM circuits DRAM2, every time each row of the second DRAM circuits DRAM2 is accessed, it is necessary to set the access period tRAS to activate the bank active signal BACT and then select one of the rows of the second DRAM circuit DRAM2 to conduct read operation for the memory cells successively over the columns and the precharge period tRP to conduct a bit line precharge operation in response to a bit line precharge signal BPRC.
Then, when each of the DRAM circuits DRAM1 and DRAM2 is accessed as described above, it is necessary to take the time tRAS from the activation to the precharge and the time tRP from the precharge to the activation for each DRAM circuit; consequently there is a disadvantage of taking a long time for testing.
FIG. 9 is a flowchart in the case where, in the conventional LSI having a plurality of, for example a synchronous type, DRAM circuits integrated therein, the two DRAM circuits DRAM1, DRAM2 are controlled in a manner such that the data is transferred to the outside thereof.
First, the memory cells of a first row of the first DRAM circuit DRAM1 are accessed sequentially over the whole columns. Next, the memory cells of a first row of the second DRAM circuit DRAM2 are accessed sequentially over the whole columns. Next, the memory cells of a second row of the first DRAM circuit DRAM1 are accessed sequentially over the whole columns. Next, the memory cells of a second row of the second DRAM circuit DRAM2 are accessed sequentially over the whole columns. The access is repeated for all of the of the following rows, from the next row to the last row, while the access to the first DRAM circuit DRAM1 and the access to the second DRAM circuit DRAM2 are alternately changed over for each row.
In this case, every time each row of one of the DRAM circuits is accessed, it is necessary to set an access period tRAS to activate the bank active signal BACT of said one DRAM circuit and to subsequently select one of the rows to conduct read operation for the memory cells successively over the columns and a precharge period tRP to conduct bit line precharge operation by a bit line precharge signal BPRC and to subsequently activate the bank active signal BACT of the other DRAM circuit. That is, every time each row of the first DRAM circuit DRAM1 is accessed, it is necessary to set the access period tRAS to activate the bank active signal BACT of the first DRAM circuit DRAM1 and to subsequently select one of the rows to conduct read operation for the memory cells successively over the columns; and the precharge period tRP to conduct bit line precharge operation by a bit line precharge signal BPRC and to subsequently activate the bank active signal BACT of the second DRAM circuit DRAM2. Similarly, every time each row of the second DRAM circuit DRAM2 is accessed, it is necessary to set the access period tRAS to activate the bank active signal BACT of the second DRAM circuit DRAM2 and to subsequently select one of the rows to conduct read operation for the memory cells successively over the columns and the precharge period tRP to conduct bit line precharge operation by a bit line precharge signal BPRC and to subsequently activate the bank active signal BACT of the first DRAM circuit DRAM1.
However, by a very fact that the time tRAS from the activation to the precharge for each DRAM circuit and the time tRP to precharge one DRAM circuit and then make other DRAM circuit active are required, as described above, when the data that was read from a DRAM circuit by alternately accessing the plurality of DRAM circuits is transferred, there arises a problem when the data is desired to be transferred in a high speed.
FIG. 10 shows a portion of a DRAM circuit corresponding to one bank of the DRAM circuit.
The memory cell array FIG. 10 comprises a sub cell array portion including a plurality of memory cells MC of a one transistor/one capacitor configuration each of which is disposed at each of cross parts that are specified by word lines WLi (WL1, WL2, . . . , WLn) arranged in a row direction and bit line pairs BLi, /BLi (BL0, /BL0, BL1, /BL1, . . . , BLn, /BLn) arranged in a column direction perpendicular to the row direction; and sense amplifiers S/A that are disposed at both sides of each of the sub cell arrays and amplify the data that was read out to the bit-line BLi or /BLi from the memory cell of the selected row, where the data is written therein or read therefrom via column switch CS that is selected by the column selection line CSLi.
As described above, in the conventional LSI circuit having a plurality of DRAM circuits integrated therein, due to the fact that the time tRAS from the activation to the precharge for each DRAM circuit and the time tRP to precharge one DRAM circuit and then make other DRAM circuit active are required, there is a disadvantage when the data that is read out from each DRAM circuit is desired to be transferred in a high speed. Moreover, there is such a disadvantage that it takes a long time to perform testing of each DRAM circuit.